The technology described herein relates to data processing systems and in particular to cache operations in data processing systems.
Many data processing systems use caches to store data locally to a processing unit or units so as to reduce the need to fetch data from and/or write data to the main memory of the data processing system.
Caches may also be used as write buffers in order to hold data being written from the cache to the main memory, or at least to the next cache in the memory system hierarchy. In this way the processing units (which are typically fast) may be decoupled from the memory system (which is typically slow). For instance, when the cache is operating to perform a “write-back” cache operation, data to be written to the memory is passed from the processing unit to the write buffer (or cache), where it is temporarily stored, before being written to the main memory at an appropriate time. In this way, the number of write operations to the main memory may be reduced as the write-back cache holds the current copy of the data and the main memory is only updated when that data is evicted from the cache.
The data storage may be implemented using virtual memory. Thus, a data item to be read from or stored in the (main) memory may be associated with a virtual memory address which must be translated to a physical memory address in order to retrieve the data from or write out the data to the (main) memory. In order to speed up the retrieval, recent translations of virtual to physical memory addresses (“VA/PA translations”) may be stored in an address-translation cache such as a translation lookaside buffer (“TLB”). So, when it is desired to write (or read, depending on the operation) data from the cache, a request may first be sent to the address-translation cache for the required physical address (“PA”). That is, whenever a virtual memory address is referenced during a write (or read) process, the address-translation cache may be checked for a quick reference to the associated location in physical memory, and if the required PA is present in the address-translation cache (a translation ‘hit’) the data may be written out to (or read from) the memory. On the other hand, when the address-translation cache does not contain the required VA/PA translation, so that a virtual memory address being searched in the address-translation cache is not found (a translation ‘miss’), a request for the associated physical memory address must be sent to the system memory management unit (“MMU”) which then retrieves the missing PA and the new VA/PA translation is stored in the address-translation cache for future use. In this event, the cache read or write operation may be stalled until the new VA/PA translation has been stored in the address translation cache.
In typical such operations, there may be strict requirements relating to the order in which the data is written to (or read from) the memory and various hazard checking rules for “reads” and “writes” to enforce this.
However, the Applicants have recognised that there can be situations where it is desired to write (e.g. write-back) cached data via an address-translation cache such as a TLB wherein the data can be written out in any order (in time). An example of this would be a write-only cache acting as a merging write buffer for a set of independent data streams in which each entry in a data stream will only be written to memory once, and the data streams will not be read until all writing has completed and all data streams are marked as complete. In this case, the data in the data stream may be written to the memory in any order (in time), as each write operation is thus independent of the next with no data sharing. One example of this situation may be when generating lists of “primitives” (also referred to as “polygons”) for use in tile-based graphics processing systems.
The Applicants believe that there is room for improvements in such situations, e.g. when writing-back cached data to a memory via an address-translation cache such as a TLB where there is no requirement on the order in which the data is written to the memory.